/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 *
 * (C) Copyright 2009
 * Michel Pollet <buserror@gmail.com>
 *
 * (C) Copyright 2012
 * Gabriel Huau <contact@huau-gabriel.fr>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/arch/s3c2440.h>
#include <asm/arch/iomux.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <netdev.h>
#include "mini2440.h"

DECLARE_GLOBAL_DATA_PTR;

static inline void pll_delay(unsigned long loops)
{
	__asm__ volatile ("1:\n"
	  "subs %0, %1, #1\n"
	  "bne 1b" : "=r" (loops) : "0" (loops));
}

int board_early_init_f(void)
{
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
	struct s3c24x0_clock_power * const clk_power =
					s3c24x0_get_base_clock_power();

	/* to reduce PLL lock time, adjust the LOCKTIME register */
	clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
	clk_power->clkdivn = CLKDIVN_VAL;

	/* configure UPLL */
	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
	/* some delay between MPLL and UPLL */
	pll_delay(100);

	/* configure MPLL */
	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);

	/* some delay between MPLL and UPLL */
	pll_delay(10000);

#else
	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
	int gpio_val = 0;

	/* set up the I/O ports */
	writel(0x007FFFFF, &gpio->gpacon);

	writel(0x00295555, &gpio->gpbcon);		
	writel(0x000007FF, &gpio->gpbup);			//0~10 pins pull up function is disabled
	gpio_val = (readl(&gpio->gpbdat) & (~0x01));
	writel(gpio_val, &gpio->gpbdat);

	writel(0xAAAAA6AA, &gpio->gpccon);
	writel(0x0000FFFF, &gpio->gpcup);			//0~15 pins pull up function is disabled
	gpio_val = (readl(&gpio->gpcup) & (~(1<<5)));
	writel(gpio_val, &gpio->gpcdat);

	writel(0xAAAAAAAA, &gpio->gpdcon);
	writel(0x0000FFFF, &gpio->gpdup);			//0~15 pins pull up function is disabled
	
	writel(0xAAAAAAAA, &gpio->gpecon);
	writel(0x00003FFF, &gpio->gpeup);			//0~13 pins pull up function is disabled
	
	writel(0x0000AAAA, &gpio->gpfcon);
	writel(0x000000FF, &gpio->gpfup);			//0~7 pins pull up function is disabled
	
	/*GPG[15:13] must be selected as Input in NAND boot mode. */
	writel(0x02A9ABBA, &gpio->gpgcon);
	writel(0x0000FFFF, &gpio->gpgup);			//0~15 pins pull up function is disabled

	/* IOMUX Port H : UART Configuration */
	gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
		IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
	gpio->gphup = 0x000006FF;


	writel(0xAAAAAAAA, &gpio->gpjcon);
	writel(0x00001FFF, &gpio->gpjup);			//0~12 pins pull up function is disabled
#endif

	return 0;
}

/*
 * Miscellaneous platform dependent initialisations
 */
int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;

	return 0;
}

int dram_init(void)
{
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
	struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();

	/*
	 * Configuring bus width and timing
	 * Initialize clocks for each bank 0..5
	 * Bank 3 and 4 are used for DM9000
	 */
	writel(BANK_CONF, &memctl->bwscon);
	writel(B0_CONF, &memctl->bankcon[0]);
	writel(B1_CONF, &memctl->bankcon[1]);
	writel(B2_CONF, &memctl->bankcon[2]);
	writel(B3_CONF, &memctl->bankcon[3]);
	writel(B4_CONF, &memctl->bankcon[4]);
	writel(B5_CONF, &memctl->bankcon[5]);

	/* Bank 6 and 7 are used for DRAM */
	writel(SDRAM_64MB, &memctl->bankcon[6]);
	writel(SDRAM_64MB, &memctl->bankcon[7]);

	writel(MEM_TIMING, &memctl->refresh);
	writel(BANKSIZE_CONF, &memctl->banksize);
	writel(B6_MRSR, &memctl->mrsrb6);
	writel(B7_MRSR, &memctl->mrsrb7);
#endif

	gd->ram_size = PHYS_SDRAM_SIZE;
	return 0;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_DRIVER_DM9000
	return dm9000_initialize(bis);
#else
	return 0;
#endif
}

#if defined(CONFIG_DISPLAY_BOARDINFO)
int checkboard(void)
{
	puts("Board: Friendlyarm mini2440\n");
	return 0;
}
#endif

